The Pb center resides on flat surfaces (terraces), not at ledges [3]; it is considered as the main source of defects at the Si(111)/SiO2 interface. It was named as Pb0 with reference to the Pb1 center on Si(100). The interface defect is amphoteric that is a donor level below mid gap and an acceptor level above mid gap. Memory structures based on nanocrystalline (NC) semiconductor have received much attention for next-generation nonvolatile memory devices due to their selleck products extended scalability and improved memory performance [4–6]. Recently, the quantum size effects caused by the channel material NC Si neglecting the interface charge

on the threshold voltage of thin-film transistors without float gate [7] and on charging the dynamics of NC memory devices [8] have been studied. Here, both the quantum size effects caused by the float gate material

NC and the interface traps effects on the retention time of memory devices are studied. Theory For p-type silicon, Poisson’s equation can be written as follows: (1) where φ(z) is the electrostatic potential, ϵ s is the dielectric constant of silicon, N A is the ionized acceptor concentrations, n i is the intrinsic density, k is the Boltzmann constant, and T is the temperature. Using the relationship and then integrating from 0 to φ s , obtain surface electric field at the side of silicon substrate see more as follows: (2) If ψ s > 0, choose the ‘+’ sign (for a p-type semiconductor), and if ψ s < 0, choose the ‘−’ sign. Poisson's equation in the gate oxide and the NC Ge layer with uniformly stored charge

density Q nc per unit area can be written as follows: (3) (4) where d nc and ϵ nc are the thickness and the average dielectric constant of NC Ge layer, respectively. Consider boundary conditions for the case of interface charge density Q it captured by the traps at Si/SiO2 interface; thus, the electric field across the tunneling oxide layer is the following: (5) where ϵ ox is the dielectric constant of SiO2. The applied gate voltage of a NC flash memory device is equal to the sum of the voltage drop across the layer of NC Ge, SiO2, and p-Si: (6) where d tox and d cox are the thickness of the tunneling oxide layer and control oxide layer, either respectively. The interface charge density is obtained by multiplying the density of interface trap states (D it) by the trap occupation probability and integrating over the bandgap [9]: (7) The Fermi-Dirac distribution function F(E) for donor interface traps is (1 + 2 exp[(E F − E)/(kT)])−1 and that for the acceptor interface traps is (1 + 4 exp[(E − E F )/(kT)])−1. The leakage current can be calculated using [10]: (8) where T(E) is the transmission coefficient calculated by solving Equation 8 using the transfer matrix method, V is the voltage drop values in the tunneling region, m* is the effective electron mass, and ħ is the reduced Planck constant.